Generally, a semiconductor chip package alone cannot receive electricity from outside to transmit or receive an electric signal, such that it is necessary to package a semiconductor chip to allow the semiconductor chip to receive the electric signal from and transmit the electric signal to the outside.
Recently, as the semiconductor chip package is manufactured in various configurations using various members such as leadframes, printed circuit boards and circuit films in consideration of reduced chip size, heat emitting capacity and improved electrically performing capacity, improved reliability and manufacturing cost.
Concomitant with recent advancement towards higher degree of integration and faster operation speed of semiconductor chips, it has become necessary to increase the number of input/output terminals (electrical leads) between the semiconductor chip and outside circuit substrate. To this end, a semiconductor chip package of multi-row leadframe mounted with leads having 2 or more rows that separately connect the chips with outside circuit is receiving attention and interest.
FIG. 1 illustrates an example of manufacturing a semiconductor device according to the prior art disclosed in the Korea patent Laid-open No. 10-2008-00387121.
According to order of the conventional semiconductor package process, after a resist film (11) is coated on the overall obverse and reverse surfaces of a lead frame material (10) constituted of Cu, a Cu alloy or an iron-nickel alloy (e.g., 42 alloy), the resist film (11) is exposed with a predetermined lead pattern and development is then carried out, thereby forming an etching pattern (12) of the plating mask. Then, the leadframe material (10) is subjected to all-over plating, and if the resist film (11) is removed, plating masks (13, 14) are formed on the obverse and the reverse surfaces {see FIG. 1 (a) to FIG. 1 (d)}.
Successively, after the entire lower surface (i.e., reverse surface side) is coated with another resist film (15), the upper surface side (i.e., the obverse surface side) is subjected to half etching by using a plating mask (13) as a resist mask. In this case, since that portion of the surface of the leadframe material 10 which is covered by the plating mask (13) is not etched, an element mounting portion (16) and a wire bonding portion (17) formed in advance by the resist film ultimately project. It should be noted that the surfaces of the element mounting portion (16) and the wire bonding portions (17) are covered by the plating mask (13) {see (e) and (f) of FIG. 1}.
Next, after removing the resist film 15 on the lower surface side, a semiconductor element 18 is mounted on the element mounting portion 16, and electrode pad portions of the semiconductor element 18 and the wire bonding portions 17 are wire bonded, the semiconductor element 18, bonding wires 20, and the wire bonding portions 17 are resin encapsulated. Reference numeral 21 denotes an encapsulating resin {see (g) and (h) of FIG. 1}.
Subsequently, the reverse surface side is subjected to half etching. At this time, the portion of the leadframe material 10 where the plating mask 14 is formed remains without being etched since the plating mask 14 acts as a resist mask. As a result, reverse surfaces of external connection terminal portions 22 and the element mounting portion 16 project. Since the external connection terminal portions 22 and the wire bonding portions 17 communicate with each other, the respective external connection terminal portions 22 (and the wire bonding portions 17 communicating therewith) are made independent and are electrically connected to the respective electrode pad portions of the semiconductor element 18. Since these semiconductor devices 23 are generally arranged in grid form and are manufactured simultaneously, they are diced and exfoliated, thereby manufacturing individual semiconductor devices 23 {see (i) and (j) of FIG. 1}.
However, with the (e) process in the above-described conventional semiconductor manufacturing process in a case when etching is carried out on the leadframe material portion 10 using the plating layer (13) on the upper surface as an etching mask, damage may be incurred by attack on the plating layer on the upper surface of the leadframe material during etching process, the damage of which may cause a fatal effect on the wirebonding and the product reliability.
Now, referring to FIG. 2 which is an enlarged view of a plating pattern portion (A portion) according to (g) process of the above-described process, where (A1) in FIG. 2 illustrates the conventional structure of plating layer (17) in FIG. 1. That is, the plating mask (17) utilized as the conventional plating mask, as illustrated in the drawing, is conventionally formed by providing, for instance, an Ni undercoat layer (24) on the upper surface of the leadframe material (10), and by further providing a noble metal plating (25). However, in the case when the etching is carried out using the plating pattern as a plating mask, the noble metal plating (25) is not eroded during etching, but the leadframe material (10) formed of copper or a copper alloy and the Ni undercoat (24) are eroded by an etching solution, as shown in (A2) and (A3) of FIG. 2. Hence, the periphery of the noble metal plating (25) assumes a foil-like shape, and is adhered to the periphery of each of the wire bonding portions (17), the element mounting portion (16), and the external connection terminal portions (22), thereby forming plating burrs (26. plating foils).
If such plating burrs (26) are present, the plating burrs (26) are exfoliated in the wire bonding process, the resin encapsulating process (i.e., molding process), and the like, causing defects in semiconductor devices including faulty wire bonding, and short-circuiting between terminals, and the like.
The conventional semiconductor manufacturing process inevitably generates plating burrs, such that it is necessary to add de-burring and cleaning processes in order to enhance the reliability.
To be more specific, the semiconductor package manufacturing method according to the prior art suffers from disadvantages in that additional processes should be carried out in which an intermediate product (i.e., the product immediately after half etching) is immersed in a water tank having a brush or an ultrasonic transducer to exfoliate the plating burrs and a cleaning process follows, thereby making the manufacturing method uneconomical. There is another disadvantage in that material loss increases due to generation of plating burrs.
There is still another disadvantage in that the plating layer using the noble metal is used as an etching mask, which in turn makes the periphery of strips noble metal plated, thereby increasing the material cost.